1. Field of the Invention
The present invention relates to a pad layout on an integrated circuit chip (IC chip). More specifically, the present invention relates to a pad layout that can reduce the noise interference in an integrated circuit.
2. Description of Related Art
As the performance of an IC chip constantly increase, the working frequency of electronic signals transmitting in an IC chip increases gradually as well. However, when the working frequency of the electronic signals is increased to a high frequency level, for example over giga-hertz, the electronic signals in the IC chip are easily subjected to severe noise interference.
FIG. 1 is a perspective view of a conventional IC chip. FIG. 2 is a top view of the IC chip in FIG. 1. Referring to FIG. 1 and FIG. 2, the IC chip 100 includes a substrate 200 and a metal interconnection structure 300. The metal interconnection structure 300 is formed on a surface 202 of the substrate 200, and the metal interconnection structure 300 has a pad layout 310. The pad layout 310 is located on a surface 302 of the metal interconnection structure 300, wherein the surface 302 is one which is relative far from the substrate 200.
The pad layout 310 has a grounding pad 312 and two signal pads 314, wherein the grounding pad 312 is positioned between the two signal pads 314. In addition, the conventional technology further uses a guard ring 320 to avoid the signal pads 314 from being interfered by the others. More specifically, the signal pads 314 are surrounded by the guard rings 320, and the guard rings 320 are electrically connected to the grounding pad 312 through the traces 330 respectively. Therefore, when the a grounding wire 340 is electrically connected to the grounding pad 312 and a ground (no shown) through a wire bonding process, the guard rings 320 may be electrically connected to the ground outside the IC chip 100 through the traces 330, the grounding pad 312 and the grounding wire 340.
Generally speaking, when the working frequency of the IC chip 100 is at a low frequency level, since the parasitic effects between the guard ring 320 and the ground are weak and can be negligible, the noise between the two signal pads 314 can be smoothly discharged out of the IC chip 100 via the guard ring 320, wherein the parasitic effects, for example, is the parasitic inductance of the trace 330, the grounding pad 312 and the grounding wire 340. Therefore, when the electronic signal is at the low frequency level, the conventional design of the guard rings 320 can protect these two signal pads 314 from being interfered by the noise.
However, when the working frequency of the IC chip 100 is at a high frequency level, the above parasitic effects, like the parasitic inductance of the trace 330, the grounding pad 312 and the grounding wire 340 for example, are strong and cannot be ignored. More specifically, since the two guard rings 320 both are connected to the grounding pad 312 via the traces 330 respectively, if these two guard rings 320, these two traces 330, the grounding pad 312 and the grounding wire 340 are considered as an integrated circuit, then the total parasitic inductance of the integrated circuit will increase as the working frequency of the IC chip 100 increases.
According to the above description, when the total parasitic inductance exceeds a threshold, the noise of the adjacent two signal pads 314 cannot be smoothly discharged to the ground outside the IC chip 100 via the guard rings 320. That means when the working frequency of the IC chip 100 is at the high frequency level, these guard rings 320 used to protect the signal pads 314 can not perform well. Therefore, the high frequency electronic signals transmitted through these signal pads 314 are easily interfered by the noise. Accordingly, the conventional design of the metal interconnection structure 300 may easily worsen the performance of the IC chip 100.